ADDER CIRCUITS - HALF ADDER AND FULL ADDER

Adder Circuits - An Introduction 

Arithmetic operations are a part of the information processing tasks carried out by digital computers.

The most basic arithmetic operation is the binary addition i.e., the addition of two binary digits. The binary addition consists of four possible operations: 0 + 0 = 0, 0 +1 = 1, 1 + 0 = 1, and 1 + 1 = 10. The input bits are called augend and addend. The first three operations produce a single output bit called sum. The last operation produces a two-bit sum output in which the most significant bit is called carry. 

Figure 1: BINARY ADDERS

Binary Adder is a combinational circuit that performs the arithmetic operation of addition with binary numbers. A combinational circuit that performs the addition of two bits is called a half adder.  A combinational circuit that performs the addition of three bits (two input bits and a previous carry) is called a full adder.

Half Adder
A logic circuit for the addition of two one-bit binary numbers is referred to as a half adder. The half adder accepts two binary digits on its inputs which are designated as augend and addend. It produces two binary digits on its outputs which are designated as the sum and carry. The truth table for the half adder is shown in figure 2. 

Figure 2: Truth Table of Half Adder

The simplified Boolean functions for the two outputs can be obtained directly from the truth table in three steps. The steps are, 
1. Find the 1's in the sum and carry output column by looking into the truth table.
2. Find its corresponding binary values of inputs and convert it into product terms.
3. Write the final expression by summing all product terms as the sum of products form.

The boolean expression for the sum and carry outputs of half adder are,

                          S = A'B + AB'

                          S = A ⊕ B

                          C = A.B

The sum output of the half adder can be generated with an Exclusive-OR gate and the carry output can be generated using an AND gate. 

Figure 3: Logic Diagram of Half Adder

The logic diagram of a half adder is shown in figure 3. A half adder can be implemented with an Exclusive-OR gate and an AND gate.

Further Reading: Implementation of Half Adder with NAND gates

Full Adder
A logic circuit for the addition of three one-bit binary numbers is referred to as a full adder. The full adder accepts three binary digits on its inputs which are designated as augend, addend, and a carry from the previous least significant position. It produces two binary digits on its outputs which are designated as the sum and carry. The truth table for the half adder is shown in figure 4. 

Figure 4: Truth Table of Full Adder

The Boolean expression for the two outputs can be obtained directly from the truth table and then can be simplified.
The sum output is given by,

S = A'B'C_i + A'BC_i’ + AB'C_i' + ABC_i       

S = A' (B'C_i + BC_i') + A (B'C_i' + BC_i) 

       [A ⊕ B = A'B+AB'and  A ⊕ B = AB+A'B']

S = A' (B ⊕  C_i) + A (B ⊕ Ci)

S = A ⊕ B ⊕ C_i

The carry output is given by, 
C_O = A'BC_i + AB'C_i + ABC_i' + ABC_i  
[A + A = A, So add two ABC_i terms to the expression]
C_O = A'BC_i + AB'C_i + ABC_i' + ABC_i + ABC_i + ABC_i 
                          [Group terms for simplification]

C_O = (A'+A)BC_i + (B'+B)AC_i + (C_i'+C_i )AB

                           [A + A' = 1]

C_O = (1)BC_i + (1)AC_i + (1)AB                

                          [1.A = A]

C_O = BC_i + AC_i + AB            

Figure 5: Logic Diagram of Full Adder

The logic diagram of a full adder is shown in figure 5. A full adder can be implemented with an Exclusive-OR gate, AND gates and an OR gate. 

Further Reading: Implementation of Full Adder with Half Adders
Also, read 

Difference between synchronous and asynchronous sequential circuits

Difference between combinational and sequential circuits