Implementation of Full adder with Half adders

A combinational circuit that performs the addition of three bits (two input bits and a previous carry) is called a full adder. 
A full adder can be implemented with an Exclusive-OR gate, AND gates and an OR gate. 
Implementation of Full adder with Half adders

It can also be implemented with two half adders (A combinational circuit that performs the addition of two bits is called a half adder. ) and one OR gate, as shown in figure 1. The boolean expressions for the full adder are derived as follows.
The sum output is given by,
S = A ⊕ B ⊕ C_i

The carry output is given by, 
C_O = A'BC_i + AB'C_i + ABC_i' + ABC_i 
                          [Group terms for simplification]
C_O = A'BC_i + AB'C_i + (C_i'+C_i )AB                                                        [A + A' = 1]
C_O = A'BC_i + AB'C_i + (1)AB 
                          [1.A = A]
C_O = A'BC_i + AB'C_i + AB

                          [Group terms for simplification]

C_O = (A'B + AB')C_i + AB

                          [A ⊕ B = A'B+AB']

C_O = (A ⊕ B )C_i + AB

C_O = (A ⊕ B )C_i + AB

Figure 1: Implementation of Full adder with Half adders