Implementation of Half Adder with NAND gates

NAND Gate

The NAND gate is said to be a universal gate because any digital circuit can be implemented and constructed with it.

NAND gates are easier to fabricate with electronic components and are the basic gates used in all IC digital logic families. A convenient way to implement a Boolean function with NAND gates is to obtain the simplified Boolean function in terms of NAND logic.

Suggested Reading: Adder Circuits - Half adder and Full adder

Implementation of Half Adder using NAND gates

A combinational circuit that performs the addition of two bits is called a half adder. The boolean expression for the sum and carry outputs of half adder are,

                          S = A'B + AB'

                          S = A ⊕ B

                          C = A.B

The sum output of the half adder can be generated with an Exclusive-OR gate and the carry output can be generated using an AND gate. 

The simplified expression in terms of NAND logic is implemented. The logic diagram of EXOR gate using the minimum number of NAND gates is shown in the figure below.

Implementation of EXOR Function using NAND Gates

The implementation of half adder can be combining the implementation of EXOR and AND function with NAND gates. The number of NAND gates required to implement a half adder is five. The following logic diagram shows the implementation of a half adder with NAND gates.

Implementation of Half Adder with NAND gates

Also, read 

Difference between synchronous and asynchronous sequential circuits

Difference between combinational and sequential circuits